The invention pertains to memory cells and arrays of memory cells which are particularly well suited to support bit serial arithmetic.
Bit serial arithmetic is useful for integrated circuit design in many applications, including CAD applications. This is because bit serial math circuitry takes up less space on an integrated circuit die. Such circuitry requires support circuitry which can do various data storage and manipulation functions in order to interface properly with other systems such as computer-aided design software. Such functions include parallel-to-serial and serial-to-parallel data format conversion, pipeline data storage, variable-length delays for various data words to insure synchronization with operations by other portions of the bit serial circuitry, or combinations of the above-noted functions.
The prior art includes universal shift registers which can do some subset of the required functions to support operations by bit serial arithmetic such as parallel-to-serial conversion and serial-to-parallel conversion. Also, delay lines are known for performing synchronization functions. However, no circuitry exists which can perform all of the support functions necessary to perform bit serial arithmetic.
Accordingly, a need has arisen for a new type of memory cell and a new arrangement of memory cells which can be operated to provide the necessary support functions for pipelined bit serial arithmetic.